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Novel Uvlsi Mos Transister Design

IP.com Disclosure Number: IPCOM000041232D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Fredericks, E Hsu, L [+details]

Abstract

A new design for an FET in which the gate oxide and gate electrodes are formed within a trench between the source and drain regions is described. This structure, as seen in the figure, eliminates the source to drain leakage problem that is well known in the art and provides for increased switching speed and circuit density. A further advantage is the planar surface topology that facilitates the metallization and interconnection of the FETs.