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Phase-Locked Loop Center Frequency Adjustment System

IP.com Disclosure Number: IPCOM000041270D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Call, MG Corner, GW Grindel, DR [+details]

Abstract

A processor is used to adjust the center frequency of the VCO (voltage-controlled oscillator) portion of a phase-locked loop. The automatic adjustment of the center frequency of the VCO portion of the phase-locked loop (PLL) 10 uses a digital-to-analog converter (DAC) 11 to set the current IRFR. Processor 12 sets latch A to 0. A nominal INPUT signal is applied to the phase detector input of PLL 10. Since the IRFR current is 0, the SET output of comparator B is high. Processor 12, in response to the high SET signal, increases the count stored in latch A any number of times until the output of the low pass filter D is equal to the reference voltage VRFR at E, at which time the SET output of comparator goes low.