Browse Prior Art Database

Sequencing Surge Block/Resistor Bed Biasing Scheme

IP.com Disclosure Number: IPCOM000041296D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bellis, RF Keeler, DG Klimanis, VD Palmer, RR Shen, MN [+details]

Abstract

This sequencing surge block/resistor bed biasing scheme shows two ways to prevent the large surging current during power sequencing. This surging current may exist if the most positive power supply is accidentally grounded or temporarily lost during chip operation. In a common P-resistor bed the subcollector bed (Fig. 1) is usually connected to the most positive power supply, 3.4 V. If the 3.4 V power supply is grounded either due to power sequencing or other reasons, there is 1.7 V across the P-N diode D formed by the P-resistor and EPI layer and a large surging current I1 will flow from 1.7 V to ground as the N+ subcollector provides a low resistance path. This situation is aggravated since there may be thousands of these types of beds existing in a typical VLSI chip. One solution (Fig.