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Inverter Chain Test Structure

IP.com Disclosure Number: IPCOM000041319D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Berger, HH [+details]

Abstract

For test purposes, representative basic circuits of a monolithic (digital) design are connected in the form of inverter chains (e.g., through special masks). If one of these basic circuits of the chain fails, the whole chain fails (no or incorrect signal transmission), so that individual defects can be detected, localized (by scanning) and analyzed in a very large number of basic circuits. This principle is used for an MTL/I2L (Merged Transistor Logic) memory. The single cell of such a memory consists of two cross-coupled MTL inverters. Fig. A shows the equivalent circuit diagram of the MTL cell structure with the two inverters T1, T2 and T1', T2'. The injectors T1, T1' of the inverters are connected to a bit line pair BL0, BL1. The common emitters of T2, T2' are connected to the word line WLn.