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Process for Multi-Level Interconnection for Vlsi Devices

IP.com Disclosure Number: IPCOM000041337D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

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Aboelfotoh, MO [+details]


This article describes an improved metal multi-level interconnection process, which results in increased yield for integrated circuit structures of both bipolar transistors and field-effect transistors. Referring to Fig. 1, a first interconnecting layer 14 of a metal, such as aluminum, is deposited to a thickness of 8,000 to 10,000 angstroms over a silicon substrate 10 covered by an insulating layer of silicon dioxide 12. Utilizing conventional lithographic and etching techniques, the interconnected aluminum is selectively removed in non-desired areas, leaving portions 15 which form the conductive interconnection paths between devices and regions in the integrated circuit, as shown in Fig. 2.