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Battery Back-Up With Defined Input Level

IP.com Disclosure Number: IPCOM000041347D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Groves, JO Neville, MH [+details]

Abstract

The circuit shown provides input voltage to random-access memory (RAM) 1 at a defined level equal to the source voltage Vi while having battery 3 as an auxiliary or back-up source of power. Diode 5 isolates battery 3 when Vi is at normal level. Diode 7 isolates battery 3 from circuit elements other than RAM 1. Inductor 9 is alternately driven and allowed to discharge in oscillations controlled by transistor 11. Inductor 9 charges capacitor 13, across RAM 1, until the potential across capacitor 13 is at Vi, after which coil 9 is shunted through diode 14. The other circuit elements constitute an oscillator to control transistor 11. Low power memories, such as complementary metal oxide semiconductor (CMOS) memories, can be supported by batteries when in an unaccessed mode, but require substantial currents when in use.