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Content-Addressable Memory Cell Having Only Six Transistors

IP.com Disclosure Number: IPCOM000041384D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Aipperspach, AG Wu, PT [+details]

Abstract

A content-addressable memory (CAM) cell has a four-FET latch and only two transfer FETs. The gates of the transfer FETs are connected to complementary write/compare lines for each word. The drawing shows a matrix of CAM cells and their peripheral circuits. A typical matrix size is 128 cells wide (128 words) by 20 cells high (20 bits/word). During standby, all write/compare lines W1-W4 are at ground potential, and all bit-compare lines are precharged to +8.5V via FETs such as 7 and 8. A 20-bit input word is simultaneously compared with all 128 stored words in the column dimension. If a match occurs, the bit-line pair corresponding to that column (e.g., B1, B2) remain precharged high. A miscompare discharges the bit-line pair.