Browse Prior Art Database

Busy Bit Concept for Two-Port Memory

IP.com Disclosure Number: IPCOM000041429D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Dill, FH [+details]

Abstract

This publication describes a busy bit concept for a two-port memory. This technique involves the addition of one bit per word on the two-port memory for providing an internal handshake mechanism whereby access control is passed. This mechanism also provides a means of having highly encoded memory protection. The quasi-two-port memory was originally proposed as a means of supporting bit mapped displays. In this mode the secondary port is read-only and the primary port is a conventional read/write port. This is satisfactory for displays which are an output device and which do not modify the contents of the file they are displaying. It is clear that the concept of a second asynchronous port is very powerful outside of the display arena, particularly if the second port can be made read/write.