Browse Prior Art Database

Word Line Clamp Circuit

IP.com Disclosure Number: IPCOM000041470D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Scheuerlein, RE [+details]

Abstract

A simplified word line clamp circuit is provided which allows tighter word line pitch and requires less semiconductor substrate surface area by selectively using a first word line as an effective ground path for a device associated with a second word line. As shown in the figure, the ground connection to the source of transistor T7 is provided by the first word line WL1. It can be seen that when NOR decoder 10 is not selected, even with isolation devices T1 and T5 turned on, transistors T2, T4 and T6 are turned off, trapping charge on the gate electrodes of transistors T3 and T7 to hold T3 and T7 on. With both T3 and T7 on both word lines WL1 and WL2 are grounded. When NOR decoder 10 is selected, transistors T2, T4 and T6 are turned on. The voltage pulse OWL1 rises and word line WL1 is driven up through T2.