Single-Phase Clocked CMOS Latch
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
A latch made in the complementary metal-oxide-semiconductor (CMOS) technology has a reduced number of devices or transistors and reduced clock signals. Clock pulses A, B and C are applied to the latch such that C is 1 or high if and only if A and B are 0 or low, i.e., C = A . B . Also, transistors P1 and P2 are P channel devices, and all other transistors are N channel devices. As shown in the figure, if A or B is high, thus, C is low and transistor N4 is off, and if the input IN2 or IN1, respectively, is high, node V goes high with the output V low and stable. When A or B is high again and IN2 or IN1, respectively, is low, node V goes low with the output V high and stable. It can be seen that transistor N4 is always off when a signal from IN1 or IN2 is being applied to node V.