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Storage Compression for Indirect Threaded CODE Machines

IP.com Disclosure Number: IPCOM000041488D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue


Related People

Garyet, DC Lotspiech, JB [+details]


Described is a method for compressing the address thread of an indirect threaded code language by keeping a table of the most commonly used addresses and referring to those addresses in the thread by a single-byte index into the table. The single-byte table indices are distinguished from double-byte direct address references by the state of their low-order bit. (The low-order bit is preferred for a status bit because frequently, in a 16-bit word machine, the direct address reference must be aligned on a 16-bit boundary, requiring the low-order bit to be zero for those references.) Indirect threaded code machines, of which the most popular are those based on the language FORTH, employ a new technology for implementing microcode which may possibly become a preferred technology.