Edge-Triggered Sampling Logic Circuit for Synchronous Systems
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
This logic circuit samples a data input and provides a data output with low skew with respect to an input gate that runs continuously at one-half the rate of the synchronous speed of the system. It is useful in applications which require a wide data valid "window" from data which may be highly skewed. Alternative methods require a clock pulse to sample and latch the highly skewed data to present a wide data valid "window". It is often difficult to propagate a narrow clock pulse and to fit it entirely under highly skewed data. A typical embodiment of the logic circuit is shown in Fig. 1. Fig. 2 shows the (idealized) waveforms involved. The logic shown in Fig. 1 follows the general form of Boolean Algebra defined below: Therefore, for Fig. 1: 1. Output = 0 = ( A + I ) .