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Diagnosis of Self-Test Failures

IP.com Disclosure Number: IPCOM000041493D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
McAnney, WH [+details]

Abstract

The technique uses signature superposition and is applicable to any self-test structure containing a repetitive pattern generator and a separate linear fault signature register, as shown in Fig. 1. In test mode, a parallel random pattern source 22 is used to broadside load the SRLs (shift register latches) 16 of each logic chip 10 on a module with pseudorandom stimuli. Following a sequential cycling of the machine clocks to capture the test results, the SRLs 16 are unloaded into a multiple input signature register (MISR) 24, simultaneously loading the next set of pseudorandom stimuli from the source 22. Each test can be symbolically represented by Scan, C1, C2, ..., Cn, where Scan represents the parallel loading (and simultaneous unloading) of stimuli into the SRLs and where Ci represents toggling of machine clock i.