Browse Prior Art Database

Load Isolator

IP.com Disclosure Number: IPCOM000041512D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Plass, DW Scheuerlein, RE Tamlyn, R Walker, WW [+details]

Abstract

Threshold-voltage-modifying arsenic and boron implants are provided in the channel of load isolator devices connected to the sense nodes of a sense amplifier to improve the performance of, e.g., N channel field-effect transistor dynamic random-access memories. The arsenic implant is preferably the same as the depletion device implant commonly used in these memories, and the boron implant is preferably the same as the high capacitance implant that is commonly used to enhance storage node junction capacitance. In Fig. 1, a first load isolating device 10 is connected between a first sense node SN1 of a sense amplifier 12 and a first bit/sense line BL1, and a second load isolating device 14 is connected between a second sense node SN2 of amplifier 12 and a second bit/sense line BL2.