Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Disclosed is an inverting driver circuit which supplies a given level output and utilizes 5.0- and 1.7-volt power supplies. A clamping mechanism is provided at the output to prevent beta degradation of some emitter input receivers. This circuit also includes a tri-state input which creates a high impedance state at the output when desired. The clamp is designed to hold the base of the Darlington transistor (NodeA-) at about 4.4 volts; the output would therefore have a maximum of 2.9 volts (N N 2 VBE's down). The clamp mechanism uses the 1.7- volt supply and a resistor divider to turn on the clamping transistor T2 when Node A reaches 4.4 volts. The Schottky barrier diode SBD1 is included in the clamping circuit to prevent reliability problems in a portion of the operating region.