High Speed Emitter Coupled Logic Counter
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
A programmable synchronous counter capable of operating at a clock rate of about 250 MHz is disclosed. Existing designs for high frequency counters emphasize minimization of hardware and generality of use. Typically, the counter uses standard master-slave flip-flops with all outputs buffered to yield a high number of fan-outs. This factor results in a decrease in the maximum operating frequency. Fig. 1 is a block diagram of one bit of the counter and is composed of four independent latches to create a master-slave latch with a toggle enable and a reset input. The counter bit is arranged as two separate master-slave flip-flops so that QM and Q-M, the master flip-flop outputs, are generated essentially simultaneously and the slave sections can be immediately clocked.