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Optimum Lateral PNP Transistor

IP.com Disclosure Number: IPCOM000041544D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Gaur, SP Huang, Y Tsang, PJ Young, PW [+details]

Abstract

This optimum lateral PNP transistor is designed for high Beta (b) high punch-through voltage, and low avalanche multiplication. These three desirable features are achieved by an optimum choice of emitter, base and collector impurity profiles, as seen in Fig. 1, in conjunction with the use of sidewall technology to define the basewidth. A cross-section of the device is shown in Fig. 2. Fabrication of the device starts with a P-type semiconductor substrate 1 with a heavily doped N-type layer 2. A lightly doped N-type epitaxial layer 3 is grown over the substrate 1. Isolation regions 4 and 5 isolate the device and define the base contact. The base contact region 6 receives a heavy N-type doping. P-type polysilicon 7 is put on the surface of the epitaxial layer, patterned, and covered with silicon dioxide 9.