Method for Making Submicron Dimensions in Structures Using Sidewall Image Transfer Techniques
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
It is desirous to make submicron feature sizes with a conventional (about 2.0 mm) lithography system. Specifically, it is desirable to make about 0.5 mm long gates for FET devices. The basic idea is to use a sidewall stud of submicron width as a mask for etching the underlying layers. In this way, the sidewall image dimension is "transferred" to them. Previously such a transfer could prove to be cumbersome. A much simpler technique has been devised and is illustrated in Figs. 1 - 8. It consists of creating a Si3N4 sidewall against a standard resist edge on top of a silicon substrate 10 having a silicon dioxide layer 12, polysilicon layer 14 and silicon dioxide layer 16. The Si3N4 layer 20 is plasma deposited over resist pattern 18, so that the temperature of the wafer will not exceed 240ŒC (Fig. 3).