Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
During the course of electrically contacting semiconductor areas or in making vias, a hole is opened in the insulation to either the semiconductor or to a metallurgy which, in turn, electrically contacts the semiconductor. Vertical walls are generated with a reactive ion etching step. In field-effect transistor technology contouring of such edges is effected by using high P doped phosphosilicate glass and heating to 1000ŒC or higher to obtain some flow and thereby rounding the sharp edges. The present process shows how such electrical contacting can be effected without the use of high-phosphorus phosphosilicate glass and high temperature heating. The Fig. 1 structure shows a P type semiconductor body 10 having an N type region 11 formed in one surface thereof.