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MTL/I2L Memory Cell

IP.com Disclosure Number: IPCOM000041587D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Heimeier, H Klein, W Klink, E Wernicke, FC [+details]

Abstract

The memory cell consists of two cross-coupled basic MTL/I2L inverter stages forming a flip-flop. Each inverter stage comprises a lateral, injecting PNP transistor and a vertical, inverting NPN transistor. The drawing shows the basic layout of one memory cell section of a memory array. The lateral PNP transistor comprises a P zone 1 with an injector contact IC and a P zone 2 which are diffused in an N layer 3. N layer 3 forms the N base of the PNP transistor as well as the emitter of the NPN transistor. P zone 2 forms the collector of the PNP transistor as well as the base of the NPN transistor and comprises a top collector contact TC within a collector zone of the NPN transistor and a base contact of the NPN transistor.