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Recessed Oxide Isolation Having a Planar Surface

IP.com Disclosure Number: IPCOM000041641D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Jimenez, AJ [+details]

Abstract

It is desirable to form a recessed oxide isolation pattern within a silicon body wherein the pattern's top surface is planar with the top surface of the silicon body. A process which accomplishes this planarity is illustrated in Figs. 1-4. Thermal nitridation of bare silicon body 10 produces a silicon nitride (Si3N4) layer 11 of the order of 10 micrometers in thickness. A chemical vapor deposition Si3N4 layer 12 of about 50 micrometers is formed thereover. Standard lithography techniques are used to pattern the designated recessed oxide insulator areas 13, as seen in Fig. 1. Standard directional etch is used to create trench 14, as seen in Fig. 2. The etch rate ratio is assumed to be Si:Si3N4 = 10:1. An example of the reactive ion etching gas is SF6 + Cl2 + He.