Efficient Bit String Handling With Standard Processing Units
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
This article relates to the manipulation of bit strings, particularly for high resolution graphics or image handling, in data processing system. The suggested solution enhances the power of ordinary storage reference instructions in standard processing units, e.g., microprocessors. The proposed improvement is intended for a system comprising processing unit, system bus, and storage unit and having the following properties: Storage addresses identify fullwords (32-bit fields) aligned on byte boundaries. Both the processing unit register width (for address calculation) and the system address bus width are 32 bits. All address lines are set from address register contents, though 24 address lines might be sufficient to cover a useful storage size of 16 Mbytes. The system data bus is 32 bits wide.