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Multiplexed Addresses for a Two-Card Processor/Memory System

IP.com Disclosure Number: IPCOM000041711D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Livingston, DL Sucher, DJ Walk, BM [+details]

Abstract

A computer system can be implemented in which a processor and a memory are contained, respectively, on two cards interconnected by a cable assembly. To reduce system cost and improve signal integrity, it is advantageous to partition the processor/memory system in order to limit the number of signals which are passed between the cards across the cable. It is also advantageous to minimize the number of components in the entire system and to balance these components between the two cards. This improvement in function partitioning is directed to the case in which dynamic random-access memories (DRAMs) are used to implement the memory array. DRAMs require that the row addresses and column addresses by multiplexed before they are latched by the memory chips.