Browse Prior Art Database

ECL to NMOS Receiver

IP.com Disclosure Number: IPCOM000041735D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Hoover, RA Murray, JP [+details]

Abstract

The ECL (Emitter Coupled Logic) Receiver is a device which provides the chip designer with a simple means of translating ECL voltage level signals (typically between -3.0 and 0.0 volts) to NMOS voltage levels on board the NMOS chip itself. The circuit requires no special mask steps to fabricate. In addition, there is no need for any supply. The circuit can be added to existing NMOS designs easily and will displace any off-chip circuitry which is currently used to provide ECL to NMOS voltage translation. ECL circuitry is used primarily in high-speed applications, since typical gate propagation delays are less than 2 ns. Real-time processing functions as well as fast floating point arithmetic operations are often implemented in the technology for this reason.