Memory Address Driver Noise Compensation Method
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
A method is described for wiring an array card in such a way as to minimize the effect of the coupling noise between adjacent address pins in array modules. The method can be described with the help of Figs. 1 and 2. Fig. 1 shows the wiring of typical address lines on an array card. Depicted are three address bits which drive three adjacent pins on several modules. For each address, the two drivers are used in order to reduce the loading per driver. The top driver is "true", and the lower driver is the address "complement". This is done to reduce the simultaneous switching of each driver. The three "true" drivers are connected to modules 1-6, and the "complement" drivers are connected to modules 7-12. Each capacitor represents the coupling capacitance between the adjacent array module pins.