Contention Resolution Between Two Processors
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
In a system wherein a maintenance processor is much slower than the host processor, a contention resolution method is embodied in order to prevent the information collected by the maintenance processor from becoming obsolete before it could intervene with regard to the host CPU. The control registers placed in the host CPU and activated by both processors are controlled by the maintenance processors on a MODIFY operation based on a masking concept. As shown on Fig. 1, two processors executing different tasks communicate with each other. The information transfer in both directions is possible if each processor has a readable and a writable register respectively writable and readable by the other. These facilities are located in a bus-to-bus adapter comprising the common read/write register.