Incremental Model Development for Timing Analysis
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Timing Analysis [*] requires the development of an entire model of a hardware system at every level of Engineering Change (EC) and the re-evaluation of the entire system's logic path delays. The method illustrated in the figures, creates a model which includes only the logic and paths affected by the EC and required by a Timing Analysis program. The method minimizes a path delay tracing run and the volume of output data that the designer must evaluate. Further, the data that is provided is only that data which is significant to the changes which were made in the design. There are two basic algorithms in the Incremental Timing Analysis (ITA) process.