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Improved Technique for Stuck Fault Testability Measurement

IP.com Disclosure Number: IPCOM000041866D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Iverson, JH Marks, LV [+details]

Abstract

Electronic logic fault simulation is performed during the preparation of test patterns. These patterns are used during manufacture to detect and isolate failing units. Fault simulation models the response of each of a number of fault machines (a machine with one internal point fixed at zero or one) and the known good machine to a series of stimuli or patterns. When a pattern is reached where the good machine and fault machine differ at a primary output (good machine outputs "one", fault machine outputs "zero", or vice versa), that fault is said to be tested. The input pattern and the identity of the differing outputs are said to test the fault. In a logic configuration which contains latching or memory outputs, the value of one or more outputs driven by latching elements may be undefined (at value U) at any given time.