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Browse Prior Art Database

High Density Multi-Chip Chip Site

IP.com Disclosure Number: IPCOM000041876D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Feinberg, I Kraus, CJ Stoller, HI [+details]

Abstract

Logic and memory chips are placed adjacent to each other on the same dual-chip site with non-changeable direct connections between the logic and memory chips and with engineering change (EC) connections being provided through the module only for the other logic chip connections whereby high density packaging and high performance are achieved. For cache applications where some chips (RAMs or ROMs) communicate exclusively with the chips adjacent to them on the module, as shown by L1 and L2 in the figure, the interconnecting lines can be placed directly on the surface of the module. Such direct surface interconnections greatly reduce the lengths of these lines as compared to using buried levels of connecting lines within the multiple-layer module which is the usual practice.