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True/Complement Generator

IP.com Disclosure Number: IPCOM000041901D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Coelho, F Nuez, JP [+details]

Abstract

The true/complement generator shown in the drawing is to be used for providing the true and complement values 0 and 0/-/, respectively, of input address bits, to an address decoder for selecting word lines of a memory. These signals are sequenced to prevent undesired selections of word lines due to the simultaneous up levels of 0 and 0/-/ during their transient periods. The generator comprises two identical circuits 1 and 2 providing signals 0/-/ and 0, respectively, from the signal on input IN. The input signal is applied to circuit 2 through an inverting stage. Circuit 1 has a feedback path comprising of resistor bridges R2, R1 and R4, R3 which are connected to the 0 output in circuit 2. Circuit 2 has the same resistor bridge arrangement connected to output 0/-/ of circuit 1.