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Integrated LSSD Clock and Reset Control

IP.com Disclosure Number: IPCOM000041918D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Brown, MD Reetz, DD [+details]

Abstract

Use of level sensitive scan design (LSSD) logic chips requires added external logic for power-on reset (POR) and clocking. The figure shows circuitry to overcome this disadvantage. POR and clocking circuitry is entirely contained on the chip. POR is the standard pulse normally applied to circuitry. The nonoverlapping clock generator is the usual circuit found in LSSD literature. The timing circuitry consists of LSSD shift register latches (SRLs) and decodes for the timing states T1-TN and is initialized during POR by forcing its SRL steering logic to the desired initial state and clocking it with the nonoverlapping clock generator. The sequencing circuit, SRLs 1 and 2, is also clocked by the nonoverlapping clock generator.