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Circuit Technique to Help Prevent CMOS Latch-Up

IP.com Disclosure Number: IPCOM000041935D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Taber, AH [+details]

Abstract

As shown in Fig. 1, a diode is placed in series with the positive voltage supply line of a P-well CMOS device. The diode normally allows supply current to flow into the device during operation but will limit reverse current flow in the event that any I/O pins rise to a higher voltage than the supply. This helps eliminate improper power sequencing from being a potential cause of latch-up in P-well CMOS devices. An example of the use of this technique is as follows. Figs. 2 through 8 show how a potential latching path may occur in P-well CMOS and how an external diode can help prevent triggering of latch-up. A typical output circuit using P-well CMOS technology may be built as shown in Figs. 2 and 3. With this configuration, a lateral parasitic PNP transistor and a vertical NPN transistor may be formed as outlined in Fig. 4.