Microcode Design of Integrated Channels for Easy Migration to Non-Integrated Channels
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Referring to Fig. 1, some computer system processors include channels that are integrated with an IPU, and a trap mechanism is is utilized to cycle steal from the IPU (Instruction Processor Unit) in order to accomplish its various functions, such as data transfer, exceptional conditions, etc. The prior-art microcode design must use hardware, shared between the CHANNEL and IPU resources, to perform the architected functions of the microcode. This prevents the IPU from performing actual instruction processing while the channel is cycle stealing. As a result, a separate channel engine could be utilized for the processors of the prior art, as the channel functions become more and more complex (as in the IBM System/370XA mode). Referring to Fig.