Illegal Logic Level Sensing Circuit
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
An illegal logic level is defined herein as the input voltage level which falls between the binary logic levels '1' and '0' and of a value sufficiently close to the threshold voltage to cause an uncertainty in the output. In order to address a cell or group of cells in a random-access memory (RAM) array, for example, logic levels '1' and '0' are applied to true and complement generators for decoding the signals. If an illegal logic level is applied, under certain conditions, the RAM array will lose its data-retention capability. Disclosed herein is a circuit which solves the above problem by detecting the illegal logic level and taking the necessary corrective action.