Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
In previously developed technologies, device capacitances were usually sufficiently large to slow down input/output (I/O) circuits. In those cases where more capacitance was needed, it could efficiently be obtained by using the capacitance of a charge-coupled storage (CCS) device or the capacitance due to the first metal level over a base diffusion. With the introduction of trench-defined transistors, CCS capacitance has been reduced significantly and the planarization techniques used for contact to first metal have minimized the base diffusion to first metal level capacitance. Accordingly, the problems of circuit design for I/O circuits in certain environments have been magnified. A desired capacitance value in a trench process involving regular devices can be achieved, but the area impact is significant in so doing. Fig.