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Two-Tier Error Correcting Code for Memories

IP.com Disclosure Number: IPCOM000041946D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Wortzman, D [+details]

Abstract

The correction ability of single error correct and double error detect (SEC/DEC) codes is improved by partitioning the memory into two regions of ECC bit positions. One region has greater than nominal correctability into which known faulty memory bits are mapped by address or data steering techniques. The other region has less than nominal correctability into which no known faulty memory bits are mapped. Conventional error correcting codes (ECCs) treat all bits of an ECC word in the same manner. The code which is described here, on the contrary, is very correctable for a few of the bits and is much less correctable for the remainder of the bits. By logically moving all known faulty bits to the high correctability region, the overall correctability of the code is improved.