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Soliton Bit-Organized Memory

IP.com Disclosure Number: IPCOM000041983D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Rajeevakumar, TV Stuck, GJ [+details]

Abstract

Organizing a memory as an array of cells based upon a soliton gate, which propagates a soliton selectively according to the bias on a transmission line, provides high margins which help ensure dependable operation. The memory cell is shown schematically in Fig. 1. Each of the sections of the device is a top view of a Josephson transmission line. The shaded areas are isolation resistors in the top electrodes of the transmission lines (N .33 L). In sections 1, 2, 4 and 7, an inductor is connected between the top electrode and ground. The groundplane forms the bottom electrode of the transmission lines. Another inductor is connected between the top electrodes of sections 5 and 3.