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True/Complement Shift-Array Multiplier

IP.com Disclosure Number: IPCOM000041991D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

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Smith, CD Ward, HT [+details]


The shift-array multiplier Fig. 1 implements part of a known algorithm that is associated with the multiplier (MPLER) decoder, the multiplicand (MPCMD) shift true/complement (T/C) gates, and the adder, (see Fig. 3 of U. S. Patent 4,228,520, for example). It uses cascode current switch logic (CCSL) and results in one-half the number of delay blocks for an array of conventional full adders. The multiplier facilitates design, layout and wiring than is otherwise the case with some other known types. The multiplier (Fig. 1) is described in a 28 x 28-bit array configuration example with a 56-bit product (XY) output. The bits X0-X27 and Y0-Y27 of the multiplicand and multiplier numbers X and Y, respectively, are located in respective registers 1 and 2.