Browse Prior Art Database

True/Complement Shift-Array Multiplier Cell

IP.com Disclosure Number: IPCOM000041992D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Smith, CD [+details]

Abstract

A true/complement shift-array multiplier cell 400 (Fig. 1) is configured in differential cascode current switch circuit technology and is compatible with the multiplier array and decoder described in the preceding article and following article, respectively. The cells are arranged in an XY matrix array, as shown in the preceding article. The bits of the multiplicand number X are associated with the columns of the array. The rows of the array are controlled by mutually exclusive sets of four control signals derived from paired successive order bits of the multiplier number Y by the decoder of the following article. The cell provides a reduction in devices and delays in comparison to other known types of cells. The cell has four series-connected cascode current switch levels 101-104.