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True/Complement Shift-Array Multiplier Decoder

IP.com Disclosure Number: IPCOM000041993D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Smith, CD [+details]

Abstract

The decoders 200 (Fig. 2) are configured in differential cascode current switch circuit technology (Fig. l) for compatibility with the multiplier array and the array's cells described in the preceding two articles. In the decoder system (Fig. 2), one decoder 200 is provided for processing each pair of successive order bits Y0/Y1, Y2/Y3, ... YN/YN+1 of the multiplier number Y which contains multiple bits, e.g., twenty-eight bits, N being 0, 2, 4,....26. The decoder 200 converts the two bits into a set of four control signals, e.g., the four control signals C(-XN), C(-XN+1), C(+XN), C(+0).