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Probabilistic Updating for Store-In Cache Cross-Interrogation

IP.com Disclosure Number: IPCOM000042030D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Krygowski, MA [+details]

Abstract

This article describes a cross-interrogate (XI) mechanism for use in a multiprocessor in which each of the plural CPUs has a private store-in cache with its private cache directory. A SCE (system control element) contains the XI mechanism and is connected between main storage (MS) and each of the CPUs in the MP. For example, in a MP having three CPUs and one SCE, there are three copy directories (CDs) in the SCE having contents respectively corresponding to the contents of the cache directories in the three CPUs. An XI operation occurs in response to any cache miss, which is any CPU request that searches its cache directory and does not find any line of data for the requested address. An XI operation searches the other two CDs (i.e.