Tapered RAM Bit Line
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
A diffused bit line for sending/receiving data between a sense amplifier and a plurality of cells of a RAM (random-access array) array is shown, in which the height of the cells furthest from the sense amplifier is increased while the width of the bit line overlying these cells is decreased a corresponding amount. Such an arrangement improves the access time between the sense amplifier and the cells furthest removed therefrom. Diffused bit lines have a significant time constant (i.e., time delays) associated with them. While various methods have been proposed to decrease this delay, these methods suffer from the common drawback of increasing the bit pitch (which correspondingly increases the chip size). The structure decreases the bit line time delay without increasing the bit pitch.