Browse Prior Art Database

Mechanism to Support Bidirectional Data Transfer Operations Using a Single Line Buffer

IP.com Disclosure Number: IPCOM000042107D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Bourke, DG Chisholm, DR Downs, ES Kurtz, HL [+details]

Abstract

Bidirectional Data Transfer Some device attachments of the IBM Series/1 processor read and write data under control from a single bidirectional Device Control Block (DCB). A DCB may direct a device to read data from storage and write data to storage from or to locations specified, sometimes implicitly, by addresses within the DCB. Support is provided here to those devices when attached to a bus architected system via the Series/1 Channel Attachment. The device handler for a bus architected (BA)/Series/1 configuration may have to construct DCBs that read from and write into the same real line of storage. This presents a problem to the line buffer mechanism in the Series/1 Channel Attachment (S/1-CA) to BA System Bus. The figure depicts the S/1-CA translation and line buffer mechanisms.