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On-Chip Fault Realignment for Reliability and Yield Enhancement

IP.com Disclosure Number: IPCOM000042109D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Ryan, PM [+details]

Abstract

On-chip permutation logic provides a very powerful method of reconfiguring (and thus repairing) memories containing faulty components. A fault-tolerant memory chip array is described having permutation logic on each chip for permuting "island" portions of each chip to different addressed logical chip rows in order to place no more than one bit from one faulty "island" into the same accessed ECC word. The use of a large number of small permutable memory units (islands) - rather than the smaller number of larger permutable memory units (chips) of some prior fault-tolerant array disclosures - permits the use of initially untested faulty memory chips and achieves faster fault realignment. Consider a memory organized as shown in Fig. 1.