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Distributed Logic Low Temperature Circuit

IP.com Disclosure Number: IPCOM000042192D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Davidson, A Kugel, LE [+details]

Abstract

Combining a low-inductance SQUID (Superconducting Quantum Interference Device) with low-capacitance high-current junctions and a multi-turn primary winding, voltage balancing the SQUID below V(min), and using a turn-on current well below Im(0), makes possible a NOR circuit with characteristics appropriate for manufacturable combinatorial logic. All necessary logic circuits for computer operation, including latches, may be implemented in NOR logic. Fig. 1 shows a distributed logic circuit 1 with one input winding 2 of five turns and a DC input winding 3 of one turn. Output 4 is to a 10 L transmission line. To improve noise immunity and design margins, it is recommended that each gate be limited to one Y input winding.