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Latchable "TRUE" and "COMPLEMENT" Signal Generator

IP.com Disclosure Number: IPCOM000042199D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Jordy, G Mosley, JM [+details]

Abstract

In many applications, particularly in connection with logic arrays, it is necessary to sample or hold a signal level for a specific time or produce the TRUE and COMPLEMENT of a signal that can be latched. One way of accomplishing this is by means of a D-type flip-flop or J-K-type flip-flop. However, these require four or five complete logic circuits and are, among other things, slow. Disclosed herein and shown schematically in the figure is a transistor circuit which can produce a latchable TRUE and COMPLEMENT of an input signal without the disadvantages mentioned. The circuit generates TRUE (or in-phase) and COMPLEMENT (or out-of-phase) outputs at nodes IP and OP, respectively, from the input signal at node IN until the address valid signal at node AV goes positive.