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Multipoint Alignment: Methods for Providing Improved Overlay Yield

IP.com Disclosure Number: IPCOM000042213D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

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Chappelow, RE Higgins, JJ Mitchell, PH [+details]


In semiconductor manufacturing, production yields are severely reduced by photolithographic overlay errors. Overlay errors are caused by many factors including masks, exposure tools and process-induced effects on the wafer. This article describes two related means for reducing overlay errors from all such sources by employing multipoint mask-to-wafer alignment schemes. The customary mask-to-wafer alignment scheme involves minimizing misalignment of wafer images and mask images at two widely separated positions on the mask-wafer pair. This procedure suffers from the fact that alignment information obtained from the two selected sites does not describe the misalignment of any of the large number of other images on the mask-wafer pair. This usually causes incorrect alignments at many other sites on the wafer.