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Carry/Sum Generation for High Speed ALU

IP.com Disclosure Number: IPCOM000042216D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

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Cannon, JW [+details]


The speed of an Arithmetic Logic Unit (ALU) is increased by reducing the number of stages of delay required by the carry and sum generator for the ALU. An ALU sum generator design is described that allows sum outputs to be generated with minimal delay after the generation of the L0-order carry. A typical ALU section will combine the carry-in from a lower order section with the bit carries generated within that section to form a resultant carry which is used to invert the sum. Here, the carry-in is allowed to bypass the logic which combines all carries. The carry-in is consequently used directly to influence the sum generator. Since the "carry-in to sum" path is quite often a critical timing path, this design can directly influence machine performance by reducing the number of stages in this path by at least one. Fig.