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Real-Time Laplacian Image Edge Detector on a Single Vlsi Chip Disclosure Number: IPCOM000042234D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

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Anastassiou, D Georgiou, CJ [+details]


This publication describes a single chip Laplacian image edge detector which can perform the Laplacian operation A0 - 1/8*(A1+A2+...+A8) on every picture element (pixel) of a 512x512 digital image in real time. The chip consists of an array MxN of processing elements (PEs) which operate in parallel. A picture is divided into regions of MxN pixels which are loaded into the chip from the picture buffer via multiple serial paths. The pixels are distributed throughout the chip so that each PE receives one pixel. The PEs consist roughly of a single-bit adder, two shift registers, two multiplexers, nine tri-state buffers to control near-neighbor communication, a latch and other control logic, as seen in Fig. 1.