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Multifunction Latches on Master Slice Fet Chips

IP.com Disclosure Number: IPCOM000042276D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03

Publishing Venue

IBM

Related People

Authors:
Hill, KL Mueller, MW [+details]

Abstract

In master slice integrated circuits, minimizing logic block count to achieve the desired function in a single integrated circuit is made difficult by the overhead necessary to provide testability. In some current LSI master slice technologies, the implemented test method requires the chip to be a level sensitive scan device (LSSD). Through the use of master-slave latches with an additional test input path on the master and certain ground rules, high levels of testability are achieved through computer-generated test patterns. This saves time and improves the quality level of the chip. However, these LSSD latches and the ground rules create non-functional circuit overhead, which, using the maximum allowed block count in a master slice, might make the design difficult to achieve in a single chip.